MPC8245LZU266D MPC8245 Integrated Processor Hardware Specifications

MPC8245LZU266D MPC8245 Integrated Processor Hardware Specifications

Part Number: MPC8245LZU266D

Brand: FREESCALE

Package: BGA

Features
Major features of the MPC8245 are as follows:
• Processor core
— High-performance, superscalar processor core
— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit
(LSU), system register unit (SRU), and branch processing unit (BPU)
— 16-Kbyte instruction cache
— 16-Kbyte data cache
— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways
— Dynamic power management: 60x nap, doze, and sleep modes
• Peripheral logic
— Peripheral logic bus
– Various operating frequencies and bus divider ratios
– 32-bit address bus, 64-bit data bus
– Full memory coherency
– Decoupled address and data buses for pipelining of peripheral logic bus accesses
– Store gathering on peripheral logic bus-to-PCI writes
— Memory interface
– Up to 2 Gbytes of SDRAM memory
– High-bandwidth data bus (32- or 64-bit) to SDRAM
– Programmable timing supporting SDRAM
– One to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices
– Write buffering for PCI and processor accesses
– Normal parity, read-modify-write (RMW), or ECC
– Data-path buffering between memory interface and processor
– Low-voltage TTL logic (LVTTL) interfaces
– 272 Mbytes of base and extended ROM/Flash/PortX space
– Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit)
– Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path
– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with
programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects
— 32-bit PCI interface
– Operates up to 66 MHz
– PCI 2.2-compatible
– PCI 5.0-V tolerance
– Dual address cycle (DAC) for 64-bit PCI addressing (master only)
– Accesses to PCI memory, I/O, and configuration spaces
– Selectable big- or little-endian operation
– Store gathering of processor-to-PCI write and PCI-to-memory write accesses
– Memory prefetching of PCI read accesses
– Selectable hardware-enforced coherency
– PCI bus arbitration unit (five request/grant pairs)
– PCI agent mode capability
– Address translation with two inbound and outbound units (ATU)
– Internal configuration registers accessible from PCI
— Two-channel integrated DMA controller (writes to ROM/PortX not supported)
– Direct mode or chaining mode (automatic linking of DMA transfers)
– Scatter gathering—Read or write discontinuous memory
– 64-byte transfer queue per channel
– Interrupt on completed segment, chain, and error
– Local-to-local memory
– PCI-to-PCI memory
– Local-to-PCI memory
– PCI memory-to-local memory
— Message unit
– Two doorbell registers
– Two inbound and two outbound messaging registers
– I2O message interface
— I2C controller with full master/slave support that accepts broadcast messages
— Programmable interrupt controller (PIC)
– Five hardware interrupts (IRQs) or 16 serial interrupts
– Four programmable timers with cascade
— Two (dual) universal asynchronous receiver/transmitters (UARTs)
— Integrated PCI bus and SDRAM clock generation
— Programmable PCI bus and memory interface output drivers
• System-level performance monitor facility
• Debug features
— Memory attribute and PCI attribute signals
— Debug address signals
— MIV signal—Marks valid address and data bus cycles on the memory bus
— Programmable input and output signals with watchpoint capability
— Error injection/capture on data path
— IEEE Std 1149.1® (JTAG)/test interface

Part Status	Active
Core Processor	PowerPC 603e
Number of Cores/Bus Width	1 Core, 32-Bit
Speed	266MHz
Co-Processors/DSP	-
RAM Controllers	SDRAM
Graphics Acceleration	No
Display & Interface Controllers	-
Ethernet	-
SATA	-
USB	-
Voltage - I/O	3.3V
Operating Temperature	0°C ~ 105°C (TA)
Security Features	-
Package / Case	352-LBGA
Supplier Device Package	352-TBGA (35x35)

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