2016年10月25日星期二

A3P1000-1PQ208M A3P1000 ACTEL Field Programmable Gate Array

A3P1000-1PQ208M A3P1000 ACTEL Field Programmable Gate Array

Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI† In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
• FlashLock® to Secure FPGA Contents Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) • I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os‡
• Programmable Output Slew Rate† and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory†
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
• True Dual-Port SRAM (except ×18) ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Category
Integrated Circuits (ICs)
Family
Embedded - FPGAs (Field Programmable Gate Array)
Manufacturer
Original  
Series
ProASIC3
Part Status
Active
Number of LABs/CLBs
-
Number of Logic Elements/Cells
-
Total RAM Bits
147456
Number of I/O
154
Number of Gates
1000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-55°C ~ 125°C (TJ)
Package / Case
208-BFQFP
Supplier Device Package
208-PQFP (28x28)
  
(FPGAs ICs) A3P1000-1PQ208M A3P1000-1PQ208

Shipping:

1. We can shipping all over the world by DHL , UPS , FedEx and EMS . The packaging is very safe and strong. If you have any special needs please nitfy me.

2. It will take around 3-5 days to reach your hands.
 
Product Type & Condition :

1. Because of the fluctuant sales situation. the stock parts are always changing and the stock list cannot be promptly updated . So,please consult the stock situation when you inquire.

 
Warranty & Guarantee :

All components we sell the quality with 30 days Return policy from the day of shipment.

 
Buyer Reading: 

1. Please confirm receipt of products if the items you received , and if the goods was damaged please contact us immediately. send the photo to us that we can check and give you best solution .
2. We only guarantee Delivery in time but we couldn't control the express delivery time. Our related sales person will be responsible to send the AWB for the delivered goods in the next workday. you can check the AWB in the website which we send to you. For the AWB you also can call to the local branch of the express company in your company.
 
 
If you have any other questions please feel free to contact us in any time !

Contact Way
Name: Fanny Young
Skype ID: mjdccm
Email: Fanny.Young@szmjd.net
Trademanager: cn200873376

Website:

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